Alpha AXP Architecture Reference Manual by Richard L. Sites, Richard T. Witek

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By Richard L. Sites, Richard T. Witek

Alpha AXP structure Reference guide

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Manipulating data in a register is almost the same for both conventions. In both, integer and floating-point data have their sign bits in the leftmost byte and their least significant bit in the rightmost byte, so the same integer and Common Architecture (I) floating-point instructions are used unchanged for both conventions. Big-endian character strings have their most significant character on the left, while littleendian strings have their most significant character on the right. • The compare byte (CMPBGE) instruction is neutral about direction, doing eight byte compares in parallel.

For example, "+" applied to G_floating operands means a G_floating add, whereas "+" applied to quadword operands is an integer add. Similarly, "LT" is a G_floating comparison when applied to G_floating operands and an integer comparison when applied to quadword operands. 3 Instruction Formats There are five basic Alpha AXP instruction formats: • Memory • Branch • Operate • Floating-point Operate • PALcode All instruction formats are 32 bits long with a 6-bit major opcode field in bits <31:26> of the instruction.

System software that supports specialpurpose dedicated applications need not provide emulation in User mode if emulation is not needed for correct execution of the special-purpose applications. 3 Opcode Qualifiers Some Operate format and Floating-point Operate format instructions have several variants. For example, for the VAX formats, Add F_floating (ADDF) is supported with and without floating underflow enabled, and with either chopped or VAX rounding. For IEEE formats, IEEE unbiased rounding, chopped, round toward plus infinity, and round toward minus infinity can be selected.

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